Performance Analysis of GaN-NW FET under Wide-Range Bias Conditions for Suppressing SCEs: PADRE Simulation Approach

Abstract

The continuous scaling of conventional Si-based transistors is increasingly limited by pronounced short channel effects (SCEs), leakage currents, and degraded electrostatic control. In this paper, we present a TCAD simulation of a Gallium Nitride (GaN) Nanowire Field-Effect Transistor (NW-FET) using the MuGFET structure definition tool and the PADRE device simulator, which solves the coupled Poisson and drift-diffusion equations. This proposed device was analyzed under 10 different drain-bias conditions (1–10 V) to investigate the impact of drain-voltage variation with respect to key performance parameters. The evaluated metrics were extracted from linear and logarithmic I–V plots, including a stable , SS value of 84-85 mV/dec, drain barrier of 6-19 mV/V, and consistent I_ON​/I_OFF of . These findings provide valuable insights into the design and optimization of next-generation energy-efficient transistors in advanced integrated circuits, particularly for low-power applications.